The present invention relates to an arrangement for coupling digital processing units (modules) of a redundantly operating multi-computer system, in which processor modules can be coupled to two external data busses. Arrangements of this type are known from DE-OS No. 27 40 056 and its counterpart, U.S. Pat. No. 4,228,496. In that patent, the processor modules are in communication with each other via two interprocessor busses operated in parallel, and a central controller i.e., a controller which is common to all modules, is provided for each of these data busses. From a reliability point of view this arrangement must be considered as unsatisfactory, because in the event of failure of one such controller, half of the available transmission channels are disabled, and the failure of more than one data bus cannot be tolerated. Furthermore, the number of modules which can be operated together is limited for loading reasons to the number of the units which can be connected to one bus.
In view of the above, it is an object of the present invention to divide the data transmission channels into a larger number of units separated from each other to provide redundancy in the event of failures and to transact the data traffic through them. This avoids any central control devices in such a way that the failure of several busses can be tolerated without impairing transmission speed and in most cases also without exclusion of digital processing units connected to these busses.